Director Programmable Fabric Intel Corporation San Jose

Job Description: • 2-minute read •
The Programmable Hardware Engineering PHE group is looking for an extremely experienced candidate to lead the core fabric design team who has had prior experience in designing core circuits for FPGAs. This position will have responsibility of working very closely with the FPGA architecture, process technology, IP, software and product planning teams in setting the strategy and execution of designing the core fabric routing and interconnect, DSP blocks and RAM blocks that results in industry leading performance/watt FPGA core fabric.

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This is a highly visible role that will have a major impact in the performance of industry leading discreet FPGAs as well as FPGA based SOCs. Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost. Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides guidance on employee development, performance, and productivity issues. Plans and schedules daily tasks, uses judgement on a variety of problems requiring deviation from standard practices. Inadequacies and erroneous decisions would cause moderate inconvenience and expense.

Qualifications

BSEE or MSEE 10+ years experienceThe successful candidate will have experience in the following areas but won't be limited to these. Deep expertise and knowledge in Routing interconnect, Configuration memory cells, SRAM design, look up tables, carry chains, register files, DSP blocks etc.Design, implementation and silicon debug experience of full custom digital circuit design blocks in 14nm/16nm and below geometries.A thorough knowledge of digital custom design, semi-custom design and synthesis, auto place and route flows.Optimization of complex digital blocks for best performance, power and cost metrics.A thorough understanding of FPGA software and IP tool flows.Work with architecture and product planning teams in developing comprehensive product requirements specifications that achieves industry leading core fabric performance in advanced technology nodes.Content expertise in RAM design and advanced DSP design.Execution driven project management experience defined by various metrics, leading and lagging indicators.Expertise in soup to nuts design from Spec to GDS and post silicon validation and debug.Highly refined organizational design capability to hire, train and develop capable engineers and managers of a large worldwide matrix organization. The successful candidate will collaborate and partner with other functional organization leaders to achieve delivery of high quality FPGAs and SOCs with fast time to market.

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