In this role, you will provide technical leadership to a memory subsystem design team comprising of dram controller, cache, switch etc. You will also be directly responsible for designing and delivering an extremely high performance cache design for the next generation of Apple application processor architecture.
The ideal candidate will have 10+ years of ASIC design experience
A demonstrated history of technical leadership
5+ years of architecture research and/or development of memory or highly interconnected system architectures
5+ years of RTL/micro-architecture definition
5+ years of research and development experience in PPA (performance/power/area) analysis
Knowledge of high performance coherent memory system or interconnect architectures
Strong cache design background including good understanding of different memory organizations and trade offs
Knowledge of high performance memory subsystem and dram controller
Very good understanding of traffic scenarios in an SOC environment and differentiation of service for them
Systems experience in characterizing performance, doing comparison studies, and documenting and publishing results
Description
Drive new memory system architectures from DRAM up. Explore architecture trade-offs in system performance, area, and power consumption. Develop interconnect (Network-on-chip - NOC) and memory hierarchies for high performance parallel computer architectures (system-on-a-chip SOC). Work with performance team to develop performance/power simulators, models and test suites. Design a memory sub-system with clients of low latency and high bandwidth; taking into account of quality-of-service, and dram availability. Understand and drive the definition of the next generation of mobile memories. Integration of IP to SOC.
Education
MSEE or related field
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