In this highly visible role, you will lead a team of talented engineers working on custom digital circuits and will work with the team to implement advanced circuit techniques to improve circuit performance, optimize dynamic/static power and support full bring up. The role will be at the center of a state-of-the-art circuit design effort, interfacing with all disciplines and have a critical impact on getting functional products to market quickly.
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The ideal candidate will have 10+ years of circuit design experience in the CPU/SOC environment.
Prior experience leading a team of engineers and proven success driving products to market.
Knowledge of high performance low power circuit design.
Experience developing SRAM Arrays and custom cells.
Knowledge of industry standards circuit and design tools.
Solid understanding of device physics and process.
Ability to conduct experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data.
Description
•Drive the development of highly optimized power efficient SRAM designs for CPU applications.
•Work with logic/architecture team to define pipeline boundaries and cache design specifications.
•Understand the complete design flow, DFT and testing aspect of the design.
•Interact with a technology team, participate in developing circuit methodology.
•Collaborate with the CAD team and drive design flow enhancements.
•Support Silicon bring up activities to hit Mass Production .
Education
BSEE/MSEE is required, PhD preferred.
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