Imagine what you could do here. At Apple, great ideas have a way of becoming great products, services, and customer experiences very quickly. Apple is leading the charge in high performance mobile computing with state of the ART SOC's announced with each of its revolutionary new product offerings. At the core of all Apple mobile SOC's, is an on chip system interconnect bus that supplies the SOC agents with their requested load and store data from on chip and off chip memories.
Key Qualifications
This position requires thorough knowledge of the ASIC design flow, front end RTL coding and Design verification, synthesis, scripting and netlist generation.
The ideal candidate will have the following background
At least 10+ years experience in ASIC design flow
Expertise in at least one of the following disciplines:
CPU load store units or BIU unit design
L1, L2, or larger on chip or off chip cache design
Coherent memory system design
SOC system bus design
Memory controller design
Networking packet based bus protocols
Proven track record of complex high performance designs in high volume production for low power applications
Design for high performance, low area, and low power
Familiarity with CDC, DFT, UPF, other Asic flow checks, and backend timing closure at hihg frequencies is a plus
Strong communication skills are a pre-requisite as the candidate will interface with a lot of different people within and outside the company
Self starter and highly motivated
Description
As a senior member of the SOC Design team you will be responsible for the following 1) Microarchitecture and design of RTL code for high performance (low latency, high bandwidth, high frequency), low area, and low power 2) Own all aspects of development design for large SOC blocks including: Internal and external IP integration, design of system bus and control bus logic for connectivity of IP blocks to main SOC infrastructure, ownership of the Integration Spec for the design project, integration and optimization of any memories and hard macros required for the block, run synthesis, netlist generation, and timing closure for the block 3) Work closely with Chip Architecture, memory system Design, Design verification, Physical Design, DFT, and power teams to achieve first tapeout success on designs 4) Develop and maintain methodology/flows/checks for designs 5) Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process
Education
MSEE or related field
Send To A Friend
Posts
