Wednesday, September 21, 2016

Director Technical Wireless RTL Design Intel Santa Clara

Job Description: • 2-minute read •
You will report to the senior director of Modem System, Baseband Algorithm and Physical Layer HW engineering and manage a team of digital design engineers that develops advanced, high bandwidth, low latency and high data rates baseband modems. You will be responsible for the definition, design, implementation and verification of the digital physical layer for 5G FPGA and ASIC modem platforms.
Watch: Career Advice
You are experienced in defining the modem architecture and provide technical guidance to the reference modelling and RTL design and verification teams. You also have experience in leading a medium sized team of highly skilled engineers.

Project deliverables include micro-architecture designs, RTL code, simulation models and reference codes, test benches and associated documentation.

You will work closely with standards and algorithm teams by providing feedback and alternatives to develop cutting edge wireless solutions and support firmware and RF teams with verification and bring-up of FPGA and ASIC modems.

You mentor senior and junior engineers in a team environment.
Qualifications
The position requires a BS, MS or PhD in Electrical or Computer Engineering or similar discipline and 15+ years of industry experience, including:
- Technical leadership in wireless communication systems
- Knowledge of wireless communications systems and standards, including LTE (FDD/TDD) and UMTS. Experience in modem design and verification.
- Management of engineering teams with more than 20 highly skilled modem HW experts
- Experiences in digital design and verification as well as and signal processing for wireless digital communication systems.
- Experience in VHDL/Verilog RTL design, simulation and verification for FPGA platforms
- Experience with revision control systems such as Clearcase or GIT
- Debug and analytic skills

Preferred technical qualifications:
- Technical leadership in LTE physical layer design
- Experience with Quartus and Synplify Pro synthesis
- Experience with scripting languages such as TCL, Python, or Perl
- Experience in VHDL/Verilog RTL design, simulation and verification for ASIC development
- Experience with VCS, Verdi, and Spyglass
- Experience with DPI-C, SystemVerilog, UVM
- Experience with C/C++, Python, Matlab and/or other simulation and modeling tools/languages
- Experience with Linux/Unix operating system

You should have a proven track record for taking projects from conception through deployment and verification as well as for technical leadership and staff development.

This role requires strong technical leadership and decision-making skills and the ability to influence across project core teams as well as other functional teams building 5G platforms. The successful candidate will have excellent communication and leadership skills and a proven ability to define, develop and drive technical execution plans with challenging schedules.
Send To A Friend
Related Posts Plugin for WordPress, Blogger...